Meet qwenGPU: Qwen3.5-2B With 45 Compiled GPU Layers That Run CUDA
qwenGPU is an experimental model that compiles a SIMT GPU directly into the weights of Qwen3.5-2B. Developer Vixhal (@TheVixhal) released it on GitHub under the MIT license. The model runs real CUDA, compiled to NVIDIA PTX, inside its own forward passes. For developers, it tests one idea: exact computation inside a pretrained LLM, not beside it.
TL;DR
- Size: Qwen3.5-2B (24 layers) along with 45 compiled GPU layers, 69 in total. Context: 262,144 tokens (base model).
- Runs on: Apple silicon, an NVIDIA GPU or a CPU, with about 16 GB of free memory. No quantized build.
- Performance: Every launch in the developer’s runs was exact; text drift is a KL of about 7e-4.
- Best: The reference interpreter matched a real NVIDIA Tesla T4 on 49 of 49 kernels.
- Worst: About 10 to 15 tokens per second on Apple MPS; Qwen-written CUDA passed 4 of 5.
What is qwenGPU?
qwenGPU is Qwen3.5-2B with 45 compiled transformer layers placed in front of Qwen’s own 24. None of those layers are trained. A compiler computes every weight.
How does a GPU fit inside model weights?
The GPU is a 4-lane SIMT machine. It has 15 registers per lane, a 4-stage pipeline, a 32-block ROM and 126 memory words. It uses only Qwen3.5’s own layer types: Gated DeltaNet linear attention and SwiGLU MLPs.
The trick is the Gated DeltaNet recurrent state. In the circuit’s heads, the gate is held open and the write strength is 1. Every key is one-hot. Each update overwrites exactly 1 row, and a one-hot query reads it back. So each row works as a memory cell.
That state holds the program ROM, registers and global memory. The README lists 16 register rows per lane, with 1 that always reads zero. That matches the 15 usable registers in the X post.
The GPU supports integer arithmetic, predicates, divergent branches and loops. It also supports shared memory, atomicAdd, __syncthreads() and warp shuffles.
What happens during a CUDA launch?
The host plays the role of NVRTC and the CUDA driver. It compiles CUDA to PTX with clang, then lowers PTX to machine blocks. It feeds the program and input arrays to the model as tokens.
From there, the model writes the launch itself. Each EXEC(b, w) token runs block b for warp w in 1 forward pass. The VAL tokens after it carry register results. Memory writes return as MEM records. The host reads results from the recurrent state and computes none of them.
In the demo video, a dot product of [1, 2, 3] and [4, 5, 6] returns 32. The model wrote that launch in 47 tokens.
Meet qwenGPU: Qwen3.5-2B with a SIMT GPU inside its weights, 45 compiled layers in front of Qwen’s own, using its Gated DeltaNet layers as registers and memory.
— vixhaℓ (@TheVixhal) November 1, 2026
It runs real CUDA in its forward passes. The host compiles the kernel to PTX and loads it, then the model writes every… pic.twitter.com/iM5IETEbIv
Does the GPU break Qwen’s text ability?
Not by the developer’s measure. The circuit is muted on text tokens, and Qwen’s own weights are unchanged. The merged model’s next-token distribution stays within a KL of about 7e-4 of the original.
How accurate is qwenGPU?
All numbers are self-reported, measured on Apple silicon with MPS in bf16:
- Every launch was exact under
--checkreplay. - The reference interpreter matched an NVIDIA Tesla T4 on 49 of 49 test kernels.
- Normal mode answered 20 of 24 sampled chat questions with GPU-computed numbers.
- Advanced mode wrote a correct kernel first try on 4 of 5 questions.
In normal mode, Qwen writes an expression like [1, 2, 3] @ [4, 5, 6] for ready-made kernels. In advanced mode, Qwen writes the CUDA kernel itself. The README warns that a 2B model’s CUDA is still unreliable.
How does qwenGPU compare with Qwenputer and Percepta?
qwenGPU uses the transformer compiler from Qwenputer by Divyansh Agrawal. Qwenputer compiles a 32-bit RISC-V CPU into Qwen3.5-4B. Percepta built a WebAssembly interpreter into a transformer with 2D attention heads in March 2026.
| Feature | qwenGPU | Qwenputer (RISC-V) | Percepta |
|---|---|---|---|
| Base model | Qwen3.5-2B, 24 layers | Qwen3.5-4B | Custom transformer with 2D attention heads |
| Machine compiled in | 4-lane SIMT GPU | 32-bit RISC-V (RV32IM + Zba + bignum) | WebAssembly interpreter |
| Programs it runs | CUDA, lowered from PTX | C and MicroPython | C, compiled to WebAssembly |
| Compiled layers | 45 | 11 | Not disclosed |
| Where state lives | Gated DeltaNet state | Gated DeltaNet state | Execution trace in context |
| Host role | Compiles CUDA to PTX, loads tokens, reads results | Loads firmware; runs no computation | Not disclosed |
| Correctness check | Interpreter matched Tesla T4 on 49 of 49 kernels | 0 mismatches in about 230,000 replayed positions | Claims millions of reliable steps |
| Reported speed | 10 to 15 tokens/s (Apple MPS) | About 3,200 trace tokens/s (L4, Triton) | 30,000+ tokens/s (CPU) |
| Text drift vs base | KL about 7e-4 | KL 6e-4 | Not applicable |
| License | MIT code; Apache-2.0 checkpoint | MIT code; Apache-2.0 weights | Not disclosed |
Zyphra AI Introduces Zyphra Hierarchical Attention (ZHA): A Path to True Subquadratic Attention
Zyphra has released Zyphra Hierarchical Attention (ZHA), a sparse attention method built around a tree-structured indexer. ZHA targets a known gap in sparse attention: the indexer that picks tokens still scans the whole context. Zyphra’s technical paper shows ZHA can be distilled into frozen pretrained models with about 4B tokens. On Qwen3.6-35B-A3B it stays close to dense attention on reasoning, agentic coding and 256K retrieval benchmarks.
TL;DR
- Size: It is a method that adds 81,920 trainable parameters to Qwen3.6-35B-A3B (about 0.00024%). Tested up to 256K context.
- Runs on: Retrofits frozen pretrained models after a 4B-token KL warmup at 32K context. Speedups come from a modeled H100 BF16 roofline. No optimized kernels released. An FP4 router variant was also tested.
- Performance: Within a few points of dense attention on 7 reasoning, coding and retrieval benchmarks.
- Best: LongBench v2 hits 63.4% (deep tree) vs 58.0% dense, using about 1.1% of keys.
- Worst: On NoPE-based Nemotron-3.5-Lightning-30B-A3B, deep-tree RULER-13 drops 25.3 points below dense.
What is Zyphra Hierarchical Attention (ZHA)?
ZHA is a sparse attention method from Zyphra that finds relevant keys by searching a tree. It keeps the full KV cache. The tree only decides which cached keys each query reads.
Fixed-state methods like SSMs and sliding windows saturate at long contexts. Fine-grained sparse methods like DeepSeek Sparse Attention score every past token with an indexer. The final attention is sparse, but the indexer still grows with the full context.
Near 1M tokens, cited work shows indexing takes 60 to 90% of layer time. ZHA makes the search itself sparse.
How does ZHA’s tree indexer work?
Building the tree
ZHA splits keys into contiguous chunks and compresses each chunk into a summary key. Summaries are grouped and compressed again, level by level. With chunk size 4, 6 levels cover 4,096 tokens per top node.
Summaries come from a small set of learned reference queries. Each reference query gives a tangent-plane estimate of a chunk’s log attention mass. The max over these planes approximates how much attention any future query would give the chunk.
How does top-p routing pick tokens?
At decode time, a query scores the top-level nodes. It keeps the smallest set holding a fraction p of estimated attention mass. It then expands only those children, repeating until it reaches raw KV entries.
Top-p makes the budget adaptive. A single-fact lookup touches few branches. A query that needs many scattered facts expands more. The first token is always kept as an attention sink.
How does ZHA perform against dense attention and MSA?
Zyphra team converted Qwen3.6-35B-A3B with 2 trees: deep (chunk 4, 6 levels) and wide (chunk 256, 1 level). Both use 16 reference queries and p = 0.95. It also trained a MiniMax Sparse Attention (MSA) indexer on 40B tokens, 10x ZHA’s budget.
| Benchmark (Qwen3.6-35B-A3B) | Dense | ZHA deep | ZHA wide | MSA |
|---|---|---|---|---|
| AIME 2026 | 93.1 | 91.2 | 90.8 | 91.7 |
| SWE-bench Verified | 67.4 | 67.4 | 68.4 | 63.6 |
| Terminal-Bench 2.1 | 49.9 | 46.7 | 53.3 | 46.1 |
| MMLU-Pro | 84.9 | 85.3 | 85.2 | 85.3 |
| GPQA Diamond | 84.8 | 85.0 | 85.0 | 83.1 |
| RULER-13 (256K) | 96.0 | 93.3 | 96.2 | 77.1 |
| LongBench v2 (thinking) | 58.0 | 63.4 | 62.4 | 49.3 |
Source: arXiv 2610.42112, Figure 5. All numbers self-reported by Zyphra.
The biggest gap is on retrieval. MSA drops to 77.1% on RULER-13, while both ZHA trees stay above 93%. On LongBench v2, the deep tree and MSA read similar key shares (1.1% vs 1%). The deep tree scores 14.1 points higher.
Across 28 tree geometries, RULER accuracy held steady when attending to 10 to 30% of keys. At fixed compression, deeper trees kept accuracy at higher sparsity. A 4-parameter model predicts RULER accuracy from geometry with 1.44-point RMSE.
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